The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip.
The testing of semiconductor chips in general is a very complex task because test devices must be fine enough in order to be coupled to the enormous number of chip signal input/output pins which are available to test the chip with a given test scheme.
Current and next generation semiconductor product chips have an increasingly large number of signal I/O stages to achieve the performance and complexity requirements imposed by the specific technical progress intended with each new generation. This trend, in conjunction with the required high quality of the products, results in the need for very costly test equipment to reach all of the signal input/output stages at the tester in order to have the stages tested adequately.
xe2x80x98Adequate testingxe2x80x99 means to enable for full parametric testing of the physical drive/receive capabilities of the driver/receiver system of an I/O stage. It should be noted that this is far more than the self-test facilities being implemented on-chip in prior art, as for example disclosed in U.S. Pat. No. 5,541,935, or in an exemplary I/O stage as depicted in FIG. 1, which will be discussed later below.
The xe2x80x98drive capability testxe2x80x99 basically means to give an answer to the question if a driver device has the physical (i.e. electrical) properties required for driving a desired voltage level reflecting one of the three states, i.e. low, high and high-impedance state, abbreviated herein as HZ-state, from the driver stage input to its output. In particular, testing the parametric specifications of a driver device consists of testing the resistance of the transistor device in pass mode, as well as in lock mode.
The receive capability of the receiver stage is essentially determined by whether the receive hysteresis has specified threshold levels LPUL (Least Positive Up Level for xe2x80x980xe2x80x99) and MPDL (Most Positive Down Level for xe2x80x981xe2x80x99) which can be realized during normal operation of the stage. If the respective latch stores a xe2x80x981xe2x80x99 and the value shall be overwritten to xe2x80x980xe2x80x99, a voltage level must be applied at its input which is smaller than the MPDL because of the hysteresis problem being present in this situation. On the other hand, if the latch stores a xe2x80x980xe2x80x99 which shall be overwritten to xe2x80x981xe2x80x99, an input voltage is required which is at least greater than LPUL. Thus, xe2x80x98full parametric testingxe2x80x99 means to qualify a respective driver/receiver stage to determine if (and to quantify, in particular, how good) the drive and receive processes can be achieved with an I/O stage.
The above mentioned test equipment required for full parametric testing is large and expensive. In particular, the coupling between test apparatus and chip is difficult because of the enormous number of I/O stages to be tested. Nearly each new chip generation requires a new expensive test apparatus in particular to test the quality of the I/O stages.
In order to simplify the full parametric chip testing a method was introduced, the so-called xe2x80x9creduced pin test methodxe2x80x9d. The basic idea used in this prior art approach is to couple an intermediate, connective device having a reduced number of pins between the test apparatus and the chip to be tested. The testing scheme was then a xe2x80x98structurized schemexe2x80x99, i.e. a scheme in which a selectively chosen subset of chip signal I/Os connected to a low pin count test apparatus and a specific set of test patterns, applied only to this test I/O interface was decided to be sufficient to test the respective chip and in particular by having the unconnected signal I/Os testing themselves by receiving their own driven value.
A prior art I/O stage is illustrated below with reference to FIG. 1. FIG. 1 shows a simplified scheme of a prior art bi-directional signal I/O stage 10 having a built-in xe2x80x98digitalxe2x80x99 self-test feature by which minimum qualitative properties of driver 18 receiver 24 system can be tested by driving both values xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 to node 14 (generally a connective pad denoted as PAD in the figures), and by receiving it correspondingly in receiver 24 and signal line 26 RDATA.
This kind of self-test, however, is of limited coverage as mentioned above with reference to U.S. Pat. No. 5,541,935, because it does not tell anything about the xe2x80x98analogxe2x80x99, i.e. the electrical properties of the I/O stage (the driver and receiver capabilities, DC-Ohm or AC-impedance, and hysteris behavior) as it will be described later below. Thus, applying this kind of built-in self-test, the driver as well as the receiver part can not be fully tested against the parametric specifications of the I/O stage like drive capability and/or receiver threshold levels.
I/O stage 10 further consists of signal line 12 DDATA as a signal input representing the logical data value (xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99) which has to be driven out by driver logic 18 to node 14 denoted as PAD as the off-chip connection thereof. Signal line 16 carries a signal denoted as ACT which is the signal input used for ACTivating and turning off the driver when signal I/O stage 10 has to be in receive mode. P-type 20 and N-type 22 output stage field effect transistors, referred to herein and denoted in the drawing as P and N (FETs) are connected to node 14 PAD.
The P and N transistor devices depicted in FIG. 1 are illustrated in a simplified manner in order to improve clarity. In reality, each device 20 and 22 consists of a number of single transistors of the I/O stage, which is in turn often called an xe2x80x98I/O bookxe2x80x99.
Receiver device 24 denoted as xe2x80x98recxe2x80x99 converts the voltage levels applied at node 14 PAD to logical xe2x80x980xe2x80x99 and xe2x80x981xe2x80x99 values at signal line 26 denoted as RDATA which is usually stored into a latch for further test evaluation but could also be carried out in a different way to the test apparatus. For simplification of the following disclosure it will be assumed that rec 24 already contains a latch function to store the test result.
Having implemented the limited self-test capability mentioned above, signal I/O stage 10 receives its own driven output signal. In this situation the off-chip connection PAD has no loading applied so that driver logic 18 may achieve the receiver threshold levels LPUL (Least Positive Up Level for xe2x80x980xe2x80x99) and MPDL (Most Positive Down Level for xe2x80x981xe2x80x99) too easily, which may result in undertesting. Further, a defect mis-aligning the detection levels of receiving stage 24 can rarely be found in the receiver area which may result in undertesting, as well.
As can be appreciated now by a person skilled in the art, due to the problems mentioned above there is a need to have all signal I/O stages connected to the above mentioned external test system in order to enable the testing for the full parametric specifications of drive and receive capability.
As mentioned in the prior art, the parametric drive capability test can be tested only with the external load connected to PAD in FIG. 1 provided by expensive external test circuitry. Without such external test circuitry, however, no test of the parametric specifications of the driver/receiver system can be performed, neither for chips constructed compatible to reduced pin technology nor for chips being incompatible with it.
It is thus an object of the present invention to improve the testing of driver and that of receiver stages, and in particular that of combined stages, and in particular that of semiconductor chip I/O stages.
Although the present invention has a very broad scope implied by its inherent technical abstractness, it will be discussed in here primarily with reference to bi-directional chip input/output (I/O) stages, since this is the most obvious technical area to apply the present invention and to draw significant technical and economical advantages immediately from it.
According to its broadest aspect, the present invention provides for a method and the respective hardware implementation for full parametric testing of the drive capability of a driver stage and the receive capability of a receiver stage implemented in an integrated circuit chip, which is characterized by the step of determining electrical properties (ie. DC-resistance, AC-impedance) of a driver stage by at least one test load implemented on the chip itself. For accomplishing this, the test load is selectively controllable according to a predetermined on-chip test scheme for forming a voltage divider circuit in which the test load causes a characteristic voltage drop usable for test evaluation. With this approach, a full parametric driver and receiver self-test can be achieved without the need of an external tester connection to the off-chip contacting pad. The test result is converted into digital form and can be used to draw quantified conclusions about the operational performance of the driver/receiver stage. Thus, any expensive off-chip test scheme is eliminated.
According to a preferred aspect of the present invention, the present invention provides for a method and the respective hardware implementation for full parametric testing of the drive capability of a driver stage and the receive capability of a receiver stage of a bi-directional combined driver/receiver stage, the driver stage consisting of a first number of xe2x80x980xe2x80x99 driving transistor devices, and a second number of xe2x80x981xe2x80x99 driving transistor devices. The subgroup is advantageously chosen such that the fraction obtained by the xe2x80x9csubgroupxe2x80x9d divided by the xe2x80x9ctotalxe2x80x9d is significantly different from 50%, a feature which is further to be referred to as xe2x80x98asymmetric controlxe2x80x99, or xe2x80x98asymmetric voltage dividerxe2x80x99. The method consists of the steps of: a) selectively controlling a subset of the first number of transistor devices for forming a respective test load for the total of the second number of transistor devices, b) generating an evaluable input voltage at a receiving device of the receiver stage reflecting the drive capability of the total of the second number of transistor devices, c) selectively controlling a subset of the second number of transistor devices for forming a respective test load for the total of the first number of transistor devices, and d) generating an evaluable input voltage at the receiving device of the receiver stage reflecting the drive capability of the total of the first number of transistor devices.
Because of the xe2x80x98splitxe2x80x99 output stage devices, a very high precision for accurate V PAD (pad voltage) level adjustments can be achieved in comparison to an analog control.
There is no need for additional, space consuming load devices; the output stage devices of P-, and N-type, respectively, are split into at least two sub-devices P1, P2 and N1, N2. Thus, they are re-used for test purposes when being controllable separately.
The test scheme is simple and is applied via the test signal I/O""s.
The test can be applied at low speed. There is no need for high performance test equipment.
The test can be applied at every packing level: at wafer level, on a single-chip module (SCM) or on a temporary chip attach (TCA), on a multiple chip module (MCM), and even at system level, when the chip is incorporated into a printed circuit board connected to whatever bus system. In the latter case, advantageously a dedicated piece of system software can be executed which controls the hardware logic according to the test scheme so as to perform the inventive test method. The software may be run triggered by service staff or in any automated form.
For implementing the inventive logic adequate to modern chip design, the first number of transistor devices advantageously consists of P-type transistors and the second number of transistor devices consists of N-type transistors, or vice versa, respectively.
The above method can advantageously be applied to situations in which the driver/receiver stage is an input/output (I/O) stage of a chip. But the inventive concept is free to be accomodated to test for an output-only stage of a chip, as well. For this purpose, the voltage level serving as a test result has to be read and evaluated by a separate signal line, instead of the already existing receiving line in the case of the combined I/O case.
As should be appreciated by a person skilled in the art, the basic concept of the present invention consists of the idea to setup, i.e. to establish a controllable xe2x80x98on-chip loadingxe2x80x99, for each signal I/O stage so that the driver as well as the receiver can be tested against the full parametric specifications without a tester pin connected to the external, connective node.
Basically, this can be achieved by adding a load device on the chip and controlling it accordingly by separate control inputs. Advantageously, however, this is achieved by re-using the transistor devices of the driver devices which are already present in the I/O stage as a voltage divider for asymetrically testing a subgroup of the P-device transistors against the total of the N-device transistors, and vice versa.
In particular, the inventive principle can be summarized as follows. The N-type and P-type devices of the driver output stage are logically split into two separate sub-devices P1, P2 and N1, N2, respectively. Both sub-devices, or sub-groups of transistors are arranged to be controlled separately by respective control inputs SELFTEST and ACT signals.
Further, a simple control logic is implemented which controls the above-mentioned device and sub-device such that the P-subdevice acts as a load for the N-device and vice versa.
A preferred dimensioning of the output stage devices"" resistance and thus of the selection of the degree of asymmetry is as follows. P1P2/N2=(VDD-VH)/VH, i.e., the total resistance of P1 and P2 (electrically connected in parallel) divided by the resistance of the N2 subgroup is the same as the voltage difference between VDD and VH divided by VH.
This relationship is defined in conjunction with the input detection level specification LPUL of the receiving device rec 24 plus some guardband and P2/N1N2=(VDD-VL)/VL, respectively.